1. Field of the Invention
This invention relates in general to microprocessors, and more particularly, to microprocessor architectures and methods for delivering precise traps in a processor executing instructions speculatively or out-of-order.
2. Relevant Background
In order to improve the overall performance of a computer processor (also called a microprocessor), modern processor architectures utilize various performance enhancing techniques such as speculative instruction execution and out-of-order instruction processing.
Recent processor architectures use a branch prediction unit to predict the outcome of conditional branch instructions thereby allowing subsequent instructions to be fetched according to the predicted outcome. These instructions are "speculatively" executed to allow the processor to make forward progress during the time the branch instruction is resolved. When the prediction is correct, the results of the speculative execution can be used as correct results, greatly improving processor speed and efficiency. When the prediction is incorrect, the completely or partially executed instructions must be flushed from the processor and execution of the correct branch initiated.
Conventional processors also execute instructions in an order determined by the compiled machine language program running on the processor and so are referred to as "in order" or "sequential" processors. In superscalar processors, multiple pipelines can simultaneously process instructions "out-of-order" where the instructions are processed in parallel in any efficient order, as long as there are no dependencies between instructions.
Although speculative execution and out-of-order processing greatly improve the performance of a processor, these techniques also increase the complexity of the processor as compared to simple sequential processors. One area of increased complexity relates to the handling of traps related to the processing of an instruction. When an error occurs in the execution of an instruction, a "trap" or "exception" is generated. These events require proper handling by invoking software or hardware instruction routines called "trap handlers."
In particular, speculative execution of instructions makes handling of traps difficult since an older instruction may initiate a trap after a younger instruction has been executed. Also, a trap can occur based on an instruction which is part of a mispredicted branch of instructions which should not have been executed.
What is needed is an apparatus and method for handling precise traps in a processor using speculative and out-of-order instruction execution.